Hiding of SysML model's "internal" ports in FMEDA [MEDNXP080]
When deriving a FMEDA from a model, all the internal ports used to connect the internal element in the SysML model are also imported in the FMEDA. These internal ports don't need any analysis, so, they should not appear in the FMEDA or should be hided, but not with a filter but as default. There are other ports, the ones representing the IC's pins or system connector's pins that need analysis of their failure modes in the FMEDA, so, they should not be hided. In the current Medini implementation, it can be selected in the cover tab to hide the ports, but this option is an all or nothing, so, when checked, the ports that represent IC's pins or connectors' pins are also hided, and when not checked, all model's ports (including the internal ones) appear in the FMEDA. Old NXP Excel ID (MEDNXP080) On 2019-06-05, Michael Soden said that the new concept discussing was already triggered internally in Medini team.
