Pin multiplexing and assigning package failure rate to ports of a model
This topic is migrated from NXP's Excel based requirement list for medini, entries MEDNXP008 and MEDNXP035. Following use case shall be supported efficiently: A semiconductor die has multiple peripheral functionalities (requiring m pins in total) which can be multiplexed out to a lesser number of device pins (n) to support different customer use cases. m>n, i.e. it is not possible to multiplex out all peripheral functionalities. E.g. the die offers an SPI interface (4 pins) or a set of 4 GPIO pins (m=4+4=8), which alternatively can be multiplexed out to 4 physical device pins (n=4). In the medini analysis, it's state of the art to distribute the total package failure rate r_total (e.g. from IEC TR 62380) equally to all x package pins. So every physical pin has failure rate of r_pin=r_total/x. The x total pins comprise the 4 pins described above. On the other side, the medini model for the device will reflect all peripheral functionalities (SPI and 4xGPIO, e.g. by 8 ports) independent of whether they are multiplexed out and used or not. That means the model has 8 ports for SPI and GPIO, although the device has only 4 physical pins for them. In general, the total number of ports of the model (p) will always be bigger than the number of device pins (x), p>x. The p ports comprise the 8 ports of SPI and GPIO. The model and the failure rate calculations must be done by a Safety Architect who is not aware about the particular future use cases of system integrators. The generic analysis has then to be configured for each particular system use case by a Field Application Engineer (FAE) or by the system integrator ofthe customer. The questions are: How can a Safety Architect efficiently calculate the failure rate of x individual pins (r_pin=r_total/x), but assign it to p model ports (p>x). How can an FAE or system integrator adjust the generic analysis so that it only includes those peripheral functionalities which are actually used (multiplexed out) in the particular target system? How to make sure that the resulting customized quantitative safety analysis only includes the pin/port failure rate of the actually used peripheral functionalities and not of those of unused (not multiplexed out) functionalities. How can a reviewer easily verify and confirm that the total package failure rate is correctly and completely assigned to x pins and the correct x-out-of-p used device die / model ports. A guideline and possibly some new features are necessary for this which can be distributed to NXP Safety Architects and FAEs.
